# Digital Design - Sayısal Tasarım Soru Çözümleri Bölüm 9

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Name
0
40
80
120
clock
rst
En
Ld
Clr_P1_P0
Ld_P1_P0
Ld_R0
state[3:0]
Data[7:0]
P1[7:0]
P0[7:0]
R0[15:0]
x
1
xx
2
4
8
2
a5
xx
8
1
ff
a5
xx
4
ff
a5
xxxx
00
ff
a5a5
www.Mohandesyar.com
00
ffff
from the publisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying, recording,
or likewise. For information regarding permission(s), write to: Rights and Permissions Department, Pearson Education, Inc., Upper Saddle River, NJ 07458.
294
www.Mohandesyar.com
CHAPTER 9
9.1
(a) Asynchronous circutis do not use clock pulses and change state in response to input changes.
Synchronous circuits use clock pulses and a change of state occurs in reponse to the clock transition.
(b) The input signals change one at a time when the circuit is stable.
(c) The circuit is in a stable state when the excitation variables (Y) are equal to the secondary variables
(y) (see F. 9.1). Unstable otherwise.
(d) The total state is the combination of binary values of the internal state and the inputs.
Y1 = x1'x2 + y1x2
9.2
y1y2
Y2 = x1y2 + x2
y1
x1x2
00
01
11
10
00
00
11
01
00
01
00
11
01
01
x1x2 : 00, 10, 11, 01, 11, 10, 00
x2
11
00
11
11
01
10
00
11
11
00
y1y2 : 00, 00, 01, 11, 11, 01, 00
x1
y2
9.3
(a)
x1
Y = x1x' 2 + (x1 + x'2)y
x2
z=y
y
(b)
y
y
x1
x1x2
00
01
11
10
0
0
0
0
1
1
1
0
1
1
y
y
x1
x1x2
00
01
11
10
0
0
0
0
0
1
1
1
1
1
x2
x2
(c)